參數(shù)資料
型號: tlc320ad56c
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
中文描述: sigma - delta模擬接口電路(Σ-Δ模擬接口電路)
文件頁數(shù): 13/38頁
文件大?。?/td> 253K
代理商: TLC320AD56C
2–1
2
2.1
The functions of the TLC320AD56C are described in the following sections.
Functional Description
Device Functions
2.1.1
The sampling (conversion) frequency is derived from the master clock (MCLK) input by equation 1.
Operating Frequencies
fs
Sampling (conversion) frequency
MCLK
512
(1)
The inverse is the time between the falling edges of two successive primary frame synchronization signals
and is the conversion period.
2.1.2
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data.
ADC Signal Channel
The input signal is filtered and applied to the ADC input. The ADC converts the signal into discrete output
digital words in 2s-complement format, corresponding to the analog signal value at the sampling time. These
16-bit digital words, representing sampled values of the analog input signal, are clocked out of the serial port
during the frame-sync interval, (DOUT), one word for each primary communication interval. During
secondary communications, the data previously programmed into the registers can be read out with the
appropriate register address, and the read bit set to 1. When no register read is requested, all 16 bits are
0 in the secondary word.
2.1.3
DIN receives the 16-bit serial data word (2’s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
current by the sigma-delta DAC comprised of a digital interpolation filter, and a digital 1-bit modulator. The
DACs differential outputs OUTP and OUTM are a current output-type, (which requires resistive loading 5k
maximum). These outputs are then connected to the external low pass filter, as shown in the application
schematics in Figure 3–7 and Figure 3–8 to complete the signal reconstruction. This filter can be
incorporated in the data access arrangement (DAA) for modem applications.
DAC Signal Channel
2.1.4
The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
Serial Interface
During the secondary frame synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3–1.
2.1.5
All register programming occurs during secondary communications, and data is latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during the secondary communications. The no-op command addresses the
pseudo-register (register 0), and no register programming takes place during this communications.
Register Programming
相關(guān)PDF資料
PDF描述
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
TLC320AD57C Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD58(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
TLC320AD58C Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD75C 20-Bit Sigma-Delta Stereo ADA Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD56CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TLC320AD56CPT 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TLC320AD57 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD57C 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD57CDW 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter