參數(shù)資料
型號(hào)： TLC320AD75C
廠商： Texas Instruments, Inc.
英文描述： 20-Bit Sigma-Delta Stereo ADA Circuit
中文描述： 20位Σ-Δ立體聲電路反傾銷協(xié)定
文件頁(yè)數(shù)： 13/43頁(yè)
文件大小： 211K
代理商： TLC320AD75C
2–1
2 Detailed Description
The sigma-delta ADC converter consists of an oversampling analog modulator and digital decimation filter.
The sigma-delta DAC incorporates an interpolation finite impulse-response (FIR) filter and oversampled
modulator. The pulse-width-modulation (PWM) digital output feeds an external low-pass filter to recover the
analog audio signal.
Two control registers configure the DAC. The attenuation register controls the attenuation range,
de-emphasis enable, and mute selection. The system register controls the data format and de-emphasis
filter-sample rate.
2.1
2.1.1
The power-down state is comprised of a separate digital and analog power down for the ADC. The power
consumption of each is detailed in the electrical characteristics section.
Power-Down and Reset Functions
ADC Power Down
The digital power-down mode shuts down the digital filters and clock generators. When the digital
power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion
process must synchronize to an input on LRCKA as well as SCLKA. Therefore, the conversion process is
not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This
synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial
synchronization. After DPD is brought high, the output of the digital filters remains invalid for 26 LRCKA
cycles which consists of group delays of the decimation and high-pass filter.
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the APD terminal is brought high, the
modulators are brought back online; however, the settling time of the modulator stage is normally 100 ms.
2.1.2
The conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected
after DPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed
LRCKA rate after the initial synchronization.
Reset Function for ADC
相關(guān)PDF資料
PDF描述
TLC320AD77C 24-BIT 96 kHz STEREO AUDIO CODEC
TLC320AD80C Audio Processor Subsystem
TLC320AD81CDBT Stereo Audio Digital Equalizer DC
TLC320AD81C Stereo Audio Digital Equalizer DC
TLC339CDB LinCMOSE MICROPOWER QUAD COMPARATORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD75CDL 制造商:Texas Instruments 功能描述:
TLC320AD77 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec
TLC320AD77C 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC
TLC320AD77CDB 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD77CDBG4 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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