參數(shù)資料
型號(hào): TLC7225CDWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24
封裝: 0.300 INCH, GREEN, SOIC-24
文件頁數(shù): 3/22頁
文件大?。?/td> 331K
代理商: TLC7225CDWG4
TLC7225C, TLC7225I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109B – OCTOBER 1996 – REVISED FEBRUARY 2001
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
ground management and layout
The TLC7225 contains four reference inputs that can be driven from ac sources (see multiplying DAC using ac
input to the REF terminals section) so careful layout and grounding is important to minimize analog crosstalk
between the four channels. The dynamic performance of the four DACs depends upon the optimum choice of
board layout. Figure 6 shows the relationship between input frequency and channel-to-channel isolation.
Figure 7 shows a printed circuit board layout that minimizes crosstalk and feedthrough. The four input signals
are screened by AGND. Vref was limited between 2 V and 3.24 V to avoid slew-rate limiting effects from the
output amplifier during measurements.
– 80
– 70
– 60
– 50
– 40
– 30
20 k
50 k
100 k
200 k
500 k
1 M
fI – Input Frequency – Hz
Isolation
dB
TA = 25°C
VDD = 15 V
VSS = – 5 V
Vref = 1.24 VPP
– 20
10 k
Figure 6. Channel-to-Channel Isolation
MSB
LSB
Terminal 1
System GND
OUTB
OUTA
VSS
REFB
REFA
AGND
DGND
OUTC
OUTD
VDD
REFC
REFD
Figure 7. Suggested PCB Layout (Top View)
相關(guān)PDF資料
PDF描述
TLC7226EDWR QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO20
TLC7226EDW QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO20
TLC7226EN QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDIP20
TLC7524EFN PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PQCC20
TLC7524EN PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PDIP16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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