參數(shù)資料
型號(hào): TLC7226CDWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDSO20
封裝: GREEN, PLASTIC, SOIC-20
文件頁(yè)數(shù): 20/21頁(yè)
文件大?。?/td> 440K
代理商: TLC7226CDWRG4
TLC7226C, TLC7226I, TLC7226M
QUADRUPLE 8BIT DIGITALTOANALOG CONVERTERS
SLAS060F JANUARY 1995 REVISED APRIL 2009
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
AGND bias for positive output offset (continued)
_
+
DAC A
AGND
DGND
TLC7226
Vref
OUTA
4
18
2
6
3
VDD
5
VSS
VI
Vbias
Digital inputs omitted for clarity.
Figure 5. AGND Bias Circuit
interface logic information
Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.
Table 2. Function Table
CONTROL INPUTS
OPERATION
WR
A1
A0
OPERATION
H
L
L
L
L
X
L
H
X
L
H
L
H
No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched
L = low,
H = high,
X = irrelevant
相關(guān)PDF資料
PDF描述
TLC7226CNE4 PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDIP20
TLC7226IDWG4 PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7226CN PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDIP20
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