參數(shù)資料
型號(hào): TLC7528CFNR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PQCC20
封裝: GREEN, PLASTIC, LCC-20
文件頁(yè)數(shù): 2/25頁(yè)
文件大小: 631K
代理商: TLC7528CFNR
TLC7528C, TLC7528E, TLC7528I
DUAL 8BIT MULTIPLYING
DIGITALTOANALOG CONVERTERS
SLAS062E JANUARY 1987 REVISED NOVEMBER 2008
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
WR
Address
Decode
Logic
Address Bus
Data Bus
D0 D7
DB7
DB0
WR
CS
DACA/DACB
TLC7528
IORQ
CPU
Z80-A
A8 A15
A
A + 1
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
8
Figure 7. TLC7528 To Z-80A Interface
programmable window detector
The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC
feedback resistors is within the limits programmed into the data latches of these devices. Input signal range
depends on the reference and polarity; that is, the test input range is 0 to Vref. The DACA and DACB data
latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the
output high.
相關(guān)PDF資料
PDF描述
TLC7528IFNR PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PQCC20
TLC7528CPWR PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7528IPW PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7528CFNRG3 PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PQCC20
TLC7528CNSR PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PDSO20
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