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參數(shù)資料
| 型號(hào)： | TLC876MDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 339K |
| 代理商： | TLC876MDW |
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
layout and decoupling
With high-frequency high-resolution converters, the layout and decoupling of the reference is critical. The actual
voltage digitized by the TLC876 is relative to the reference voltages. In Figure 22, for example, the reference
return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the
ground of the analog input, that are common mode to the REFTF, REFBF, and AIN terminals because of the
common ground, are effectively removed by the TLC876 high common mode rejection. Also, these capacitors
should be connected as close to reference terminals as possible.
High-frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops
between the analog input ground and the reference bypassing points are treated as input signals by the
converter using the reference inputs. Consequently, the reference decoupling capacitors should be connected
to the same physical analog ground point used by the analog input voltage (see the grounding and layout rules
section).
AIN
REFTF
4 V
VN1
4 V
VN2
REFBF
TLC876
Figure 22. Recommended Bypassing for the Reference
clock input
The clock input is buffered internally with an inverter powered from the DRVDD terminal, which accommodates
either 5-V or 3.3-V CMOS logic input signal swings with the input threshold for the CLK terminal nominally at
DRVDD/2.
The internal pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty
cycle variations, the recommended logic family to drive the clock input is high-speed or advanced CMOS
(HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and
fall times to support 20 MSPS operation.
The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency.
Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption.
digital inputs and outputs
Each of the digital control inputs, OE and STBY, has an input buffer powered from the DRVDD supply terminal.
With DRVDD set to 5 V, all digital inputs readily interface with 5 V CMOS logic. Using lower voltage CMOS logic,
DRVDD can be set to 3.3 V, lowering the nominal input threshold of all digital inputs to (3.3 V)/2 = 1.65 V, typically.
The digital output format is straight binary. For example, Table 1 shows the output format for voltage levels of
V(REFTS) = 4 V and V(REFBS) = 2 V.
A low power mode feature is provided such that when STBY is high and the clock is disabled, the static power
of the TLC876 drops significantly (see electrical characteristics table).
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