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參數(shù)資料
| 型號： | TLE7824G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | GREEN, PLASTIC,SOP-28 |
| 文件頁數(shù)： | 7/53頁 |
| 文件大?。?/td> | 900K |
| 代理商： | TLE7824G |
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Data Sheet
15
Rev. 3.01, 2008-04-15
TLE7824G
Operating Modes
4.5.3
SBC Stop Mode with Cyclic Wake
The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the
microcontroller with its quiescent current during its power saving mode (“Stop”). This mode is entered via SPI
command, and turns-off the integrated LIN bus transceiver, but the voltage regulator remains active.
The SBC periodically generates a wake-up “l(fā)ow” pulse at DO (“interconnect signal”) that is connected to an
interrupt input [P1.4] of the microcontroller. This period can be defined via the “cyclic wake period” bit field within
the SPI register. This pulse at DO has a length of two internal SBC cycles.
In case of a detected wake-up event via LIN message or any of the MONx pins, DO stays “l(fā)ow” until the first valid
SPI command.
Note: The window watchdog is automatically disabled once the LDO output current goes below a specified
“watchdog current threshold”, unless the SPI setting “WD On/Off” prevents this (see Figure 10).
Note: A wake-up event via LIN message or via MONx inputs can happen independently of the cyclic wake phase.
Note: The Window Watchdog starts with a “l(fā)ong open window” after a mode switch, e.g. to SBC Active Mode.
Figure 8
State Diagram “SBC Stop Mode with Cyclic Wake”
C 1)
Start Up
Power Up
SBC Active Mode
MS2
ON
Vcc
MS1
01
MS0
0 / 1
STOP: Cyclic Wake
MS2
ON
Vcc
MS1
11
MS0
1
cyclic wake-up
single“ Controller SPI -Command:
- select cyclic wake timing“ via SPI Timing Bits
- select SBC Stop Mode via SPI Mode Bits
- window watchdog activation / deactivation via SPI
[off“ once current consumption below threshold ]
C wake-up inputs
1) window watchdog activated
automatically once current
threshold is exceeded
select SBC
operating
mode
SBC Standby Mode
ON
Vcc
transition caused by:
2)
- event at MONx inputs:
=> DO low“
- LIN message
=> RxD + DO low“
[SPI indicates source]
2) wake-up via MONx inputs and
LIN message independent of cyclic
wake phase (asynchronous“)
NOTES:
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