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參數(shù)資料
| 型號： | TLV1508IPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 34/46頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | TLV1508IPWG4 |
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TLV1504, TLV1508
2.7V TO 5.5V, 10BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SLAS251A DECEMBER 1999 REVISED JANUARY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLV1504
TLV1508
I/O
DESCRIPTION
SDO
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB is presented. The output format
is MSB first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after
the CS falling edge, and successive data are available at the rising edge of SCLK and changed on
the falling edge.
When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the falling
edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK and
changed on the rising edge. (This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)
followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should be ignored.
The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit.
See the date code information section, item (2).
REFM
14
18
I
External reference input or internal reference decoupling. Tie this pin to analog ground if internal
reference is used.
REFP
15
19
I
External reference input or internal reference decoupling. (Shunt capacitors of 10
F and 0.1 F
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference is
used.
VCC
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
converter
The TLV1504/48 uses a 10-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV1508IPWR | 功能描述:模數(shù)轉換器 - ADC 10-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1508IPWRG4 | 功能描述:模數(shù)轉換器 - ADC 10-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1543 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3V 10 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| TLV1543C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| TLV1543CDB | 功能描述:模數(shù)轉換器 - ADC High Speed A/D RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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