參數(shù)資料
型號: TLV1543M
廠商: Texas Instruments, Inc.
英文描述: 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
中文描述: 3.3 V的10位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個模擬輸入
文件頁數(shù): 14/18頁
文件大?。?/td> 295K
代理商: TLV1543M
TLV1543C, TLV1543M
3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C – DECEMBER 1992 – REVISED MARCH 1995
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS
before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
MSB
LSB
C3
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
B3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Low
Level
11
16
(see Note A)
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
B1
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B0
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Must be High on Power Up
14
15
16
See Note B
(see Note A)
NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
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