參數(shù)資料
型號： TLV1548MJ
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝： CERAMIC, DIP-20
文件頁數(shù)： 6/36頁
文件大?。?/td> 676K
代理商： TLV1548MJ
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
2.7
5.5
V
Positive reference voltage, Vref + (see Note 2)
VCC
V
Negative reference voltage, Vref – (see Note 2)
0
V
Differential reference voltage, Vref + – Vref – (see Note 2)
2.5
VCC
VCC +0.2
V
Analog input voltage, VI (analog) (see Note 2)
0
VCC
V
High-level control input voltage, VIH
2.1
V
Low-level control input voltage, VIL
0.6
V
Setup time, input data bits valid before I/O CLK
↑↓, tsu(A) (see Figure 9)
100
ns
Hold time, input data bits valid after I/O CLK
↑↓, th(A) (see Figure 9)
5
30
ns
Setup time, CS
↓ to I/O CLK↑, tsu(CS)
See Figure 10
5
30
ns
Hold time, I/O CLK
↓ to CS↑, th(CS)
See Figure 10
65
ns
Pulse duration, FS high, twH(FS)
See Figure 12
1
I/O CLK
periods
Pulse duration, CSTART, tw(CSTART)
Source impedance
≤ 1 k, VCC = 5.5 V,
See Figure 14
0.84
s
Setup time, CS
↑ to CSTART↓, tsu(CSTART)
See Figure 14
10
ns
Clock frequency at I/O CLK fCLK
VCC = 5.5 V
0.1
6
10
MHz
Clock frequency at I/O CLK, fCLK
VCC = 2.7 V
0.1
2
2.81
MHz
Pulse duration I/O CLK high t H(I/O)
VCC = 5.5 V
50
ns
Pulse duration, I/O CLK high, twH(I/O)
VCC = 2.7 V
100
ns
Pulse duration I/O CLK low t L(I/O)
VCC = 5.5 V
50
ns
Pulse duration, I/O CLK low, twL(I/O)
VCC = 2.7 V
100
ns
Transition time, I/O CLK, tt(I/O) (see Figure 11 and Note 4)
1
s
Transition time, DATA IN, tt(DATA IN) (see Figure 9)
10
s
Transition time, CS, tt(CS) (see Figure 10)
10
s
Transition time, FS, tt(FS) (see Figure 13)
10
s
Transition time, CSTART, tt(CSTART) (see Figure 14)
10
s
TLV1544C, TLV1548C
0
70
Operating free-air temperature, TA
TLV1544I, TLV1548I
–40
85
°C
TLV1548M
–55
125
TLV1544C, TLV1548C
115
Junction temperature, TJ
TLV1544I, TLV1548I
115
°C
TLV1548M
150
NOTES:
2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000). The device is functional with reference (Vref+ – Vref–) down to 1
V; however, the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS
↓, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in an input dat until the minimum CS setup time has elapsed.
4. This is the time required for the I/O CLK signal to fall from VIHmax to VILmin or to rise from VILmax to VIHmin. In the vicinity of normal
room temperature, the devices function with an input clock transition time as slow as 1
s for remote data-acquisition applications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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