參數(shù)資料
型號: TLV1549IDR
廠商: Texas Instruments
文件頁數(shù): 3/19頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SER 38K 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 38k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.32mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,單極
TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Sample Cycle B
A/D
Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Hi-Z State
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
(see Note A)
(
≤ 21 μs)
Figure 6. Timing for 10-Clock Transfer Using CS
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
(see Note A)
Must Be High on Power Up
(
≤ 21 μs)
See Note B
Figure 7. Timing for 10-Clock Transfer Not Using CS
Sample Cycle B
A/D
Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
Low
Level
Hi-Z
See Note C
11
16
(see Note A)
(
≤ 21 μs)
Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21
μs)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.
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