參數(shù)資料
型號(hào): TLV1562CDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 1.27 MM PITCH, SOIC-28
文件頁(yè)數(shù): 11/41頁(yè)
文件大?。?/td> 600K
代理商: TLV1562CDW
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
external clock input (CR0.5 = 1, SYSCLK = External Clk)
The TLV1562 is designed to operate with an external clock input (CMOS/TTL) with a frequency from 100 kHz
to 14 MHz. When an external clock is used as the source of SYSCLK, the setup time from the falling edge of
RD to the rising edge of SYSCLK, ts(TRGL-ECLKH) is 5 ns minimum. The internal OSC is shut down when the
external clock mode is selected.
host processor interface
parallel processor interface
The TLV1562 provides a generic high-speed parallel interface that is compatible with high-performance DSPs
and general-purpose microprocessors. These include D(0,9), RD, WR, and INT. RD transitions from high to low
to signal the end of acquisition. The parallel I/O has its own power supply to minimize digital noise.
output data format
The output data format is unipolar binary (1023 to 0) when the device is operated in the single-ended input mode
and is bipolar (511 to –512) when the device is operated in differential input mode. The output code format can
be either binary or 2s compliment. The output data format is controlled by CR1.2.
power down
The device offers two different power-down modes: Auto power-down mode for interrupt-driven conversions
and software power-down mode for all conversion modes. All configuration information is kept intact when the
device is in software or auto power-down mode.
auto-power down for interrupt-driven conversion modes
When auto-power down is enabled, the device turns off the analog section (the converter except for the
reference network) at the falling edge of INT and resumes after the falling edge of CS (if RD is the conversion
trigger) or CSTART (if CSTART is the conversion trigger). The reference current and I/O are kept alive to ensure
a fast recovery. Average power consumption can be reduced by accessing the converter less often. Special
requirements for using this feature are:
D It is necessary to toggle CS between cycles so the converter knows when to resume.
D There is an additional delay to a conversion after the device is accessed due to the auto-power-down
control. Therefore, the time between RD (or CSTART) triggers is longer (longer RD or CSTART high time).
software power down (CR.10 = 1, software power down enabled)
In addition to the auto-power-down feature, the device has a software powerdown feature to further reduce
power consumption when the device is idle. Writing a 1 to control register bit CR1.0 puts the TLV1562 into
software power-down mode in 200 ns after CS is up. The device consumes less than 1
A when in the
power-down mode. Writing a 0 to control register bit CR1.0 wakes up the device. Conversion can start 1
s after
the device is resumed. CS must be high when the device is in power-down mode. Software power-down
operation is slower than auto-power down but is more flexible and consumes almost no power.
相關(guān)PDF資料
PDF描述
TLV1562IDWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
相關(guān)代理商/技術(shù)參數(shù)
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TLV1562IDW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10bit Programmable RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32