參數(shù)資料
型號(hào): TLV1562CDWR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 1.27 MM PITCH, SOIC-28
文件頁(yè)數(shù): 4/41頁(yè)
文件大?。?/td> 600K
代理商: TLV1562CDWR
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 2. Conversion Trigger Edge
CONVERSION
MODE
CONVERSION
TRIGGER
START OF
SAMPLING
START OF
CONVERSION
TIME
(INTERNAL CLK)
CONVERSION
TIME
(EXTERNAL CLK)
INTERRUPT
CANCELED
BY
DATA OUT
Mono
Interrupt
RD
WR
↑ or
2 SYSCLK from RD
RD
6 SYSCLK
5 SYSCLK
RD
41 ns§ from INT low
CSTART
CSTART
6 SYSCLK
5 SYSCLK
RD
41 ns§ from RD low
Dual
Interrupt
CSTART
CSTART
12 SYSCLK
10 SYSCLK
First RD
41 ns§ from RD low
Mono
Continuous
RD
WR
↑ or
2 SYSCLK from RD
RD
6 SYSCLK
5 SYSCLK
N/A
41 ns§ from RD low
Dual
Continuous
RD
WR
↑ or
7 SYSCLK from RD
RD
12 SYSCLK
10 SYSCLK
N/A
41 ns§ from RD low
CSTART works with or without CS active.
The first sampling period starts at the last RD low of the previous cycle or WR high of the configuration cycle. RD low is the falling edge of RD
and WR high is the rising edge of the WR signal. (Minimum sample/hold amp settling time = one SYSCLK, approximately 100 ns min, at Rs
1 k
).
§ Output data enable time is dependent on bus loading and supply voltage (BDVDD). For BDVDD = 5 V, the enable time is 19 ns at 25 pF, 23 ns
at 50 pF, and 25 ns at 100 pF. For BDVDD = 2.7 V, the enable time is 37 ns at 25 pF, 41 ns at 50 pF, and 56 ns at 100 pF.
The TLV1562 provides four types of conversion modes. The two interrupt-driven conversion modes are
asynchronous and are simple one-shot conversions. The auto-powerdown conversion feature can be enabled
when interrupt-driven conversion modes are used. The other two continuous conversion modes are
synchronous with the RD signal (as a clock) from the processor and are more suitable for repetitive signal
measurement. These different modes of conversion offer a tradeoff between simplicity and speed.
相關(guān)PDF資料
PDF描述
TLV1562CDW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IDWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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