參數(shù)資料
型號： TLV1562IDWRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： 1.27 MM PITCH, GREEN, SOIC-28
文件頁數(shù)： 20/43頁
文件大小： 769K
代理商： TLV1562IDWRG4
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, CS
↓ to WR↓, td(CSL–WRL)
2
4
ns
Delay time, RD
↑ to CSTART↓, td1(RDH – CSTARTL)
100
ns
Delay time, RD
↑ to CSTART↓, td2(RDH – CSTARTL)
300
ns
Delay time, WR
↑ to CSTART↓, td1(WRH – CSTARTL)
100
ns
Delay time, WR
↑ to CSTART↓, td2(WRH – CSTARTL)
300
ns
Delay time, CS
↓ to RD↓, td(CSL–RDL)
2
4
ns
Pulse duration, CS high, tw(CSH)
50
ns
Setup time, data valid to WR
↑, tsu(DATAIN)
5
ns
Hold time, WR
↑ to data invalid, th(DATAIN)
10
ns
Pulse duration RD low t (RDL)
Interrupt modes
50
ns
Pulse duration, RD low, tw(RDL)
Continuous modes
200
ns
Pulse duration, WR low, tw(WRL)
50
ns
Delay time, WR
↑ to CS↑, td(WRH–CSH)
4
ns
Delay time, RD
↑ to CS↑, td(RDH–CSH)
4
ns
Delay time, external SYSCLK
↓ to RD↓, CSTART↑, td(ECLKL–TRGL)
0
2
ns
Setup time, RD
↓, CSTART↑, to external SYSCLK↑, tsu(TRGL–ECLKH)
5
6
ns
Pulse duration CSTART low t (CSTARTL)
Auto power down = 1
800
ns
Pulse duration, CSTART low, tw(CSTARTL)
Auto power down = 0
100
ns
Delay time, INT
↓ to CS↓, td(INTL–CSL)
10
ns
External SYSCLK, 10 bit
5
5.5
Internal SYSCLK, 10 bit
6
Conversion time mono continuous/interrupt mode t
1
External SYSCLK, 8 bit
4
4.5
SYSCLK
Conversion time, mono continuous/interrupt mode, tconv1
Internal SYSCLK, 8 bit
5
SYSCLK
External SYSCLK, 4 bit
2
2.5
Internal SYSCLK, 4 bit
3
External SYSCLK, 10 bit
10
11
Internal SYSCLK, 10 bit
12
Conversion time dual continuous/interrupt mode t
2
External SYSCLK, 8 bit
8
9
SYSCLK
Conversion time, dual continuous/interrupt mode, tconv2
Internal SYSCLK, 8 bit
10
SYSCLK
External SYSCLK, 4 bit
4
5
Internal SYSCLK, 4 bit
6
External SYSCLK, 10 bit
5
5.5
Internal SYSCLK, 10 bit
6
Cycle time continuous mode RD t (RD)
External SYSCLK, 8 bit
4
4.5
SYSCLK
Cycle time, continuous mode RD, tc(RD)
Internal SYSCLK, 8 bit
5
SYSCLK
External SYSCLK, 4 bit
2
2.5
Internal SYSCLK, 4 bit
3
Mono interrupt mode sampling time or first cycle (mono interrupt or
continous mode) sampling time, ts1
0.2
1000
s
Dual interrupt mode sampling time or first cycle (dual interrupt or continuous
mode) sampling time, ts4
0.3
1000
s
Mono continuous mode sampling time, ts2
3
SYSCLK
Dual continuous mode sampling time, ts3
7
SYSCLK
Continuous mode first sampling time, t(SAMPE5)
0.45
s
Data rise time, tr(DATAOUT)
3
5
10
ns
相關(guān)PDF資料
PDF描述
TLV1570CPWG4 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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