參數(shù)資料
型號(hào): TLV1570CPWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, TSSOP-20
文件頁(yè)數(shù): 12/32頁(yè)
文件大?。?/td> 634K
代理商: TLV1570CPWRG4
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SCLK
SDIN
CS
SDOUT
FS
MUX
REFERENCE
10-BIT
SAR ADC
I/O REGISTERS
AND CONTROL LOGIC
AVDD
DVDD
AGND
DGND
MO
AIN
REF
AGND
REF+
REF–
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
14
Analog ground
AIN
20
I
ADC analog input
AVDD
15
Analog supply voltage, 2.7 V to 5.5 V
CH0 – CH7
5,4,3,2,1,
18,17,16
I
Analog input channels 0 – 7
CS
12
I
Chip select. A low level signal on CS enables the TLV1570. A high level signal on CS disables the device
and disconnects power to the TLV1570.
DGND
7
Digital ground
DVDD
6
Digital supply voltage, 2.7 V to 5.5 V
FS
8
I
Frame sync. The falling edge of the frame sync pulse from a DSP indicates the start of a serial data frame
shifted out of the TLV1570. FS is pulled high when interfaced to a microcontroller.
MO
19
O
On-chip MUX analog output
REF
13
I
Reference voltage input. The voltage applied to REF defines the input span of the TLV1570. In external
reference mode, a 0.1
F decoupling capacitor must be placed between the reference and AGND. This is
not required for internal reference mode.
SCLK
9
I
Serial clock input. SCLK synchronizes the serial data transfer and is also used for internal data conversion.
SDIN
10
I
Serial data input used to configure the internal control register.
SDOUT
11
O
Serial data output. A/D conversion results are output at SDOUT.
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TLV1570CDW 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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