參數(shù)資料
型號: TLV1570IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, TSSOP-20
文件頁數(shù): 7/32頁
文件大小: 634K
代理商: TLV1570IPW
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Channel-to-channel crosstalk
–75
dB
BW
Full power bandwidth
–1 dB full-scale input sine wave
12
15
MHz
BW
Full-power bandwidth
–3 dB full-scale input sine wave
25
MHz
BW
Small-signal bandwidth
–1 dB
15
20
MHz
BW
Small-signal bandwidth
–3 dB
35
MHz
f
Sampling rate
AVDD = 5 V
0.0625
1.25
MSPS
fs
Sampling rate
AVDD = 3 V
0.0625
0.625
MSPS
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t (SCLK) SCLK cycle time
DVDD = 5.5 V to 4.5 V
50
ns
tc(SCLK) SCLK cycle time
DVDD = 3.6 V to 2.7 V
100
tw(1)
Pulse duration, chip select
100
ns
t(s)
Sampling period
6
SLCK
cycles
t(conv)
Conversion period
10
SLCK
cycles
tsu(1)
Setup time, FS to SCLK falling edge in DSP mode
5
ns
th(1)
Hold time, FS to SCLK falling edge in DSP mode
2
ns
tsu(2)
Setup time, FS to CS falling edge in DSP mode
5.5
ns
th(2)
Hold time, FS to CS falling edge in DSP mode
9
ns
td(1)
Delay time, FS falling edge to next SCLK falling edge in DSP mode
6
ns
td(2)
Delay time, SCLK rising edge after CS falling edge in
C mode
4
ns
td(3)
Delay time, output after SCLK rising edge in
C mode and DSP
mode
10
20
ns
tsu(3)
Setup time, serial input data to SCLK falling edge
10
ns
th(3)
Hold time, serial input data to SCLK falling edge
4
ns
tr
Rise time
3
200
ns
Specifications subject to change without notice.
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