參數(shù)資料
型號(hào): TLV1571CDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: GREEN, PLASTIC, SOIC-24
文件頁數(shù): 4/33頁
文件大?。?/td> 627K
代理商: TLV1571CDW
TL
V1571,
TL
V1578
2.7
V
to
5.5
V
,1-/8-CHANNEL,
10-BIT
,
RARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTERS
SLAS170D
MARCH
1999
REVISED
JUL
Y
2000
12
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
software START conversion
external clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, INT goes low telling the host that conversion is ready to be read out. EOC is low during the
conversion and makes a high-to-low transition at the end of the conversion. The external clock is active and is used as the reference at all
times. With this mode, WR and RD should not be applied at the rising edge of the clock (see Figure 3).
Auto Powerdown
CLK
CS
WR
RD
D[0:9]
INT
EOC
Config
Data
ADC Data
t su(CSL_WRL)
th(WRH_CSH)
t su(DAV_WRH)
t h(WRH_DAV)
tc
t su(CSL_RDL)
th(RDH_CSH)
t en(RDL_DAV)
t dis(RDH_DAV)
t
t en(RDL_DAV)
01
5
6
7
15
16
OR
su(CSL_RDL)
04
5
15
t(sample)
(Channel 0)
(see Note A)
tc
t(sample)
(Channel 1)
(see Note A)
t d(EOC_RDL)
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 6. Multichannel Input Mode Conversion – Software Start, External Clock
相關(guān)PDF資料
PDF描述
TLV1571IPW 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV1571IPWR 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV1571CPWR 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
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