參數(shù)資料
型號： TLV1571CDWR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝： GREEN, PLASTIC, SOIC-24
文件頁數(shù)： 14/33頁
文件大小： 627K
代理商： TLV1571CDWR
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc(CLK)
Cycle time CLK
DVDD = 4.5 V to 5.5 V
50
ns
tc(CLK)
Cycle time, CLK
DVDD = 2.7 V to 3.3 V
100
ns
t(sample)
Reset and sampling time
6
SYSCLK
Cycles
tc
Total conversion time
10
SYSCLK
Cycles
twL(EOC)
Pulse width, end of conversion, EOC
10
SYSCLK
Cycles
twL(INT)
Pulse width, interrupt
1
SYSCLK
Cycles
t(STARTOSC)
Start-up time, internal oscillator
100
ns
td(CSH_ CSTARTL)
Delay time, CS high to CSTART low
10
ns
ten(RDL DAV)
Enable time data out
DVDD = 5 V at 50 pF
20
ns
ten(RDL_DAV)
Enable time, data out
DVDD = 3 V at 50 pF
40
ns
tdis(RDH DAV)
Disable time data out
DVDD = 5 V at 50 pF
5
ns
tdis(RDH_DAV)
Disable time, data out
DVDD = 3 V at 50 pF
10
ns
tsu(CSL_WRL)
Setup time, CS to WR
5
ns
th(WRH_CSH)
Hold time, CS to WR
5
ns
tw(WR)
Pulse width, write
1
Clock
Period
tw(RD)
Pulse width, read
1
Clock
Period
tsu(DAV_WRH)
Setup time, data valid to WR
10
ns
th(WRH_DAV)
Hold time, data valid to WR
5
ns
tsu(CSL_RDL)
Setup time, CS to RD
5
ns
th(RDH_CSH)
Hold time, CS to RD
5
ns
th(WRL_EXTXLKH)
Hold time WR to clock high
5
ns
th(RDL_EXTCLKH)
Hold time RD to clock high
5
ns
th(CSTARTL_EXTCLKH)
Hold time CSTART to clock high
5
ns
tsu(WRH_EXTCLKH)
Setup time WR high to clock high
5
ns
tsu(RDH_EXTCLKH)
Setup time RD high to clock high
5
ns
tsu(CSTARTH_EXTCLKH)
Setup time CSTART high to clock high
5
ns
td(EXTCLK_CSTARTL)
Delay time clock low to CSTART low
5
ns
td(EOC_RDL)
Delay time, conversion end to RD
↓
5
ns
NOTE: Specifications subject to change without notice.
Data valid is denoted as DAV.
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