參數(shù)資料
型號(hào)： TLV1571CPWLE
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
文件頁(yè)數(shù)： 8/26頁(yè)
文件大?。?/td> 388K
代理商： TLV1571CPWLE
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170A –MARCH 1999 – REVISED AUGUST 1999
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified analog input analysis
Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
The capacitance charging voltage is given by:
Where
Rt = Rs + Ri
Ri = Ri(ADC) + Ri(MUX)
tch = Charge time
V
C(t) +
V
S
1–e
–t
ch
RtCi
The input impedance Ri is 718 at 5 V, and is higher (~ 1.25 k) at 2.7 V. The final voltage to 1/2 LSB is given
by:
VC (1/2 LSB) = VS – (VS/2048)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1/2 LSB) = Rt × Ci × ln(2048)
V
S *
V
S
2048
+ V
S
1–e
–t
ch
RtCi
Where
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 ) × 15 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
Therefore the maximum SCLK frequency is:
Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)
(1)
(2)
(3)
(4)
(5)
(6)
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TLV1571IDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10bit 1.2 MSPS PA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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TLV1572 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN
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