參數(shù)資料
型號: TLV1571IDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: GREEN, PLASTIC, SOIC-24
文件頁數(shù): 3/33頁
文件大?。?/td> 627K
代理商: TLV1571IDW
TL
V1571,
TL
V1578
2.7
V
T
O
5.5
V
,1-/8-CHANNEL,
10-BIT
,
P
ARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTERS
SLAS170D
MARCH
1999
REVISED
JUL
Y
2000
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
11
internal clock
In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and
conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after
each conversion.
OR
Auto Power Down
CS
WR
CSTART
INTCLK
RD
D[0:9]
INT
EOC
Config
Data
ADC
Data
ADC
Data
t su(CSL_WRL)
t h(WRH_CSH)
t
d(CSH_CSTARTL)
t(sample)
(Channel 0)
(see Note A)
t su(DAV_WRH)
th(WRH_DAV)
tc
t su(CSL_RDL)
th(RDH_CSH)
t en(RDL_DAV)
t dis(RDH_DAV)
tc
t su(CSL_RDL)
t en(RDL_DAV)
t (STARTOSC)
9
10
1
0
Auto Power Down
tc
(Channel 1)
(see Note A)
t d(EOC_RDL)
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 5. Multichannel Input Mode Conversion – Hardware CSTART, Internal Clock
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