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參數資料
| 型號： | TLV1578IDAG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 30/33頁 |
| 文件大小： | 627K |
| 代理商： | TLV1578IDAG4 |
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TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
hardware configuration option
The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a
dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control
registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single
channel input mode, and hardware start of conversion using CSTART.
ADC conversion modes
The TLV1571/ TLV1578 provides two conversion modes and two start of conversion modes. In single channel
input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the
TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these
modes in more detail.
Table 1. Conversion Modes
MODES
START OF
CONVER-
SION
OPERATION
COMMENT–SET BITS
CR0.D(2–0) FOR INPUT
Single
Channel
Input
CR0.D3 = 0
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
Repeated conversions from a selected channel
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
Repeated conversions from a selected channel
WR rising edge to start sampling initially. Thereafter, sampling occurs at the rising
edge of RD.
Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse is generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Channel
Sweep
CR0.D3 = 1
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
One conversion per channel from a predetermined sequence of channels
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
One conversion per channel from a sequence of channels
WR rising edge to start sampling
ADC proceeds to sample next channel at rising edge of RD. Conversion begins
after 6 clocks and lasts 10 clocks
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Single channel input mode repeatedly samples and converts from the channel until WR is applied.
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