參數(shù)資料
型號(hào)： TLV2548(中文)
廠商： Texas Instruments, Inc.
英文描述： 2.7V to 5.5V, 12-Bit, 200KSPS, 8 Channel, Low Power, Serial Analog-to-Digital Converters with Auto Power Down(2.7V-5.5V,12位,200KSPS,八通道,低功耗,自動(dòng)掉電的串行ADC)
中文描述： 2.7V至5.5V，12位，高達(dá)200ksps，8通道，低功耗，串行模擬到數(shù)字轉(zhuǎn)換器與自動(dòng)斷電（為2.7V至5.5V，12位，處理速度高達(dá)200ksps，八通道，低功耗，自動(dòng)掉電的串行ADC）的
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 1612K
代理商： TLV2548(中文)
==1999-8-24==
P&S
ooá|′μ×ó1é· YóDT1
==30-17==
P &S
oo á|′μ×ó1é· YóDT1
μ :
ot±±ooêD×μèa· 15o
P&Sí í :
http://www.p8s.com
D :
ooêD70020D
óê±à:
430079
μ°:
( 86) ( 027￡87493500 87493506
′
( 86) ( 027) 87491166, 87493497
5.2
í1¤×÷ìt
×￠
1
￡oμ±ê1ótê3 êê±￡′óóúóá
REFP
μ1μ￡aêèμ1×aaè
1
￡¨
111111111
111
￡D óúóá
REFM
μ1μêèμ1×aaèá￡¨
000000000000
￡￡μ±ù×μíá
2V
￡¨
V
REFP
￡-
V
REFM
￡-
1
￡ê±÷tèü1¤×÷￡μêμìDùêêóá ￡
×￠
2
￡oaêê±óêèDo′ó
V
IH max
μá
V
IH min
ò′ó
V
IL max
éyá
V
IH min
ùDèμê± ￡úy3￡êò ü￡óú3ì
êyY2éˉó|ó￡¨úaDó|óD￡′ D÷oí
A/D
×a÷· úà￠′|àí ÷ ó￠3′|￡úêèê±ó
ì±ê±yá
1
|ì
s
μé÷té±￡31|ü ￡
MIN
NOM
MAX
UNIT
Supply voltage, V
CC
Positive external reference voltage input, V
REFP
(see Note 1)
Negative external reference voltage input, V
REFM
(note Note 1)
Differential reference voltage input, V
REFP
V
REFM
(see Note 1)
Analog input voltage (see Note 1)
2.7
3.3
5.5
V
2
V
CC
V
0
2
V
2.5
V
CC
V
CC
+0.2
V
0
V
CC
V
High level control input voltage, V
IH
Low-level control input voltage, V
IL
Rise time, for CS, CSTART SDI at 0.5 pF, t
r(I/O)
Fall time, for CS, CSTART SDI at 0.5 pF, t
f(I/O)
Rise time, for INT, EOC, SDO at 305 pF, t
r(Output)
Fall time, for INT, EOC, SDO at 30 pF, t
f(Output)
2.1
V
0.6
V
4.76
ns
2.91
ns
2.43
ns
2.3
ns
MIN
NOM
MAX
UNIT
Transition time, for FS, SCLK, SDI, t
t(CLK)
Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active),
t
su(CS-SCLK)
Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),
t
h(SCLK-CS)
Delay time, delay from CS falling edge to FS rising edge, t
d(CSL-FSH)
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), t
d(SCLK16F-CSH)
Setup time, FS rising edge before SCLK falling edge, t
su(FSH-SCLKF)
Hold time, FS hold high after SCLK falling edge, t
h(FSH-SCLKF)
Pulse width, CS high time, t
wH(CS)
SCLK cycle time,
V
CC
= 2.7 V to 3.6V, t
c(SCLK)
SCLK cycle time,
V
CC
= 4.5 V to 5.5V, t
c(SCLK)
Pulse width, SCLK low time, t
wL(SCLK)
Pulse width, SCLK high time, t
wH(SCLK)
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1), t
su(DI-SCLK)
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1), t
h(DI-SCLK)
Delay time, delay from CS falling edge to SDO valid, t
d(CSL-DOV)
Delay time, delay from FS falling edge to SDO valid, t
d(FSL-DOV)
Delay time, delay from SCLK rising edge (FS is active) or SCLK falling edge (FS=1) SDO valid, t
d(CLK-DOV)
Delay time, delay from CS rising edge to SDO 3-stated, t
d(CSH-DOZ)
Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC falling edge,
t
d(CLK-EOCL)
Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, t
d(EOCH-DOZ)
Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLK to
INT falling edge (when FS active), t
d(SCLK-INTL)
Delay time, delay from CS falling edge to INT rising edge, t
d(CSL-INTH)
Delay time, delay from CS rising edge to CSTART falling edge, t
d(CSH-CSTARTL)
Delay time, delay from CSTART rising edge to EOC falling edge, t
d(CSTARTH-EOCL)
Pulse width, CSTART low time, t
wL
(CSTART)
Delay time, delay from CS rising edge to EOC rising edge, t
d(CSH-EOCH)
Delay time, delay from CSTART rising edge to CSTART falling edge, t
d(CSTARTH-CSTARTL)
Delay time, delay from CSTART rising edge to EOC falling edge, t
d(CSTARTH-EOCL)
Delay time, delay from CSTART rising edge to INT falling edge, t
d(CSTARTH-INTL)
5
ns
25
ns
5
ns
0.5
7
SCLKs
0.5
SCLKs
0.5
SCLKs
0.5
SCLKs
100
ns
67
ns
50
ns
20
30
ns
20
30
ns
25
ns
5
ns
1
25
ns
1
25
ns
1
25
ns
1
25
ns
1
25
ns
1
50
ns
3.5
μ
s
1
50
ns
100
ns
1
50
ns
μ
s
0.8
1
50
ns
μ
s
ns
3.6
5
10
3.5
μ
s
Operating free-air
T
A
TLV2544C/TLV2548C
0
70
C
temperature,
TLV2544I/TLV2548I
40
85
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV2548CDW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KSPS SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV2548CDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV2548CDWR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV2548CDWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV2548CPW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200kSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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