參數(shù)資料
型號: TLV2553IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數(shù): 10/29頁
文件大?。?/td> 603K
代理商: TLV2553IPW
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
18
www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
1
2
3
5
4
6
1
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB+1
LSB
Hi–Z State
2
3
D6
D5
D4
D3
D2
D1
D0
D6
D5
D7
8
7
D7
MSB
MSB–2
MSB–1
4
5
6
7
D4
D3
MSB–4
MSB–3
D2
D1
MSB–6
MSB–5
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Initialize
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
MSB
1
2
3
5
4
6
1
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB+1
LSB
2
3
D6
D5
8
7
D7
Low Level
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB–2
MSB–1
4
5
6
7
D4
D3
MSB–4
MSB–3
D2
D1
MSB–6
MSB–5
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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