OVERVIEW
HARDWARE RESET
PLL START-UP
SOFTWARE POWER DOWN
miniDSP
DIGITAL CONTROL SERIAL INTERFACE
I2C CONTROL MODE
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
The TLV320ADC3101 is a flexible, low-power, stereo audio ADC device with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. The device integrates a host of features to reduce cost, board space, and power consumption in
space-constrained, battery-powered, portable applications.
The TLV320ADC3101 consists of the following blocks:
Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)
Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)
Register-configurable combinations of up to six single-ended or three differential audio inputs
Fully programmable PLL with extensive ADC clock-source and divider options for maximum end-system
design flexibility
Communication to the TLV320ADC3101 for control is via a two-wire I2C interface. The I2C interface supports
both standard and fast communication modes.
The TLV320ADC3101 requires a hardware reset after power up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320ADC3101 may not respond properly to register reads/writes.
When the PLL is powered on, a start-up delay of approximately 10 ms occurs after the power-up command of the
PLL and before the clocks are available to the TLV320ADC3101. This delay is to ensure stable operation of the
PLL and clock-divider logic.
By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit
block can be controlled by writing to the appropriate control register. This approach allows the lowest
power-supply current for the functionality required. However, when a block is powered down, all of the register
settings are maintained as long as power is still being applied to the device.
The TLV320ADC3101 features a miniDSP core which is tightly coupled to the ADC. The fully programmable
algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access to the
digital stereo audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The ADC
miniDSP has 512 programmable instructions, 256 data memory locations, and 128 programmable coefficients.
Software development for the TLV320ADC3101 is supported through TI's comprehensive PurePath Studio
software development environment, a powerful, easy-to-use tool designed specifically to simplify software
development on Texas Instruments miniDSP audio platforms. The graphical development environment consists
of a library of common audio functions that can be dragged and dropped into an audio signal flow and graphically
connected together. The DSP code can then be assembled from the graphical signal flow with the click of a
mouse. See the TLV320ADC3101 product folder on
www.ti.com to learn more about PurePath Studio software
and the latest status on available, ready-to-use DSP algorithms.
The TLV320ADC3101 supports the I2C control protocol and is capable of both standard and fast modes.
Standard mode is up to 100 kHz and fast mode is up to 400 kHz. When in I2C control mode, the
TLV320ADC3101 can be configured for one of four different addresses, using the pins I2C_ADR1 and
I2C_ADR0, which control the two LSBs of the device address. The 5 MSBs of the device address are fixed as
0011 0 and cannot be changed, while the two LSBs are given by I2C_ADR1:I2C_ADR0. This results in four
possible device addresses:
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