參數(shù)資料
型號: TLV320AIC10IGQE
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: MICRO, PLASTIC, BGA-80
文件頁數(shù): 33/57頁
文件大?。?/td> 454K
代理商: TLV320AIC10IGQE
4–5
4.3.10 Power Supply
4.3.10.1 Low-Power Mode (set control register bit D7 to 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Power dissipation
All sections on, VDD = 3.3 V
39.3
mW
I
(analog)
Supply current
All sections on, AVDD = 3.3 V
9.7
mA
IDD (analog)
Supply current
All sections on, AVDD = 5 V
11.2
mA
I
(digital)
Supply current
All sections on, AVDD = 3.3 V
2.3
mA
IDD (digital)
Supply current
All sections on, AVDD = 5 V
4.9
mA
4.3.10.2 Normal Operation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Power dissipation
All sections on, VDD = 3.3 V
48.5
mW
All sections on, AVDD = 3.3 V
13.6
mA
I
(analog)
Supply current
All sections on, AVDD = 5 V
14.8
mA
IDD (analog)
Supply current
Power down, AVDD = 3.3 V
3
A
Power down, AVDD = 5 V
11
A
All sections on, AVDD = 3.3 V
1.1
mA
IDD (digital)
Supply current
All sections on, AVDD = 5 V
2.3
mA
IDD (digital)
Supply current
Power down, AVDD = 3.3 V
0.15
mA
Power down, AVDD = 5 V
0.6
mA
4.4
Timing Requirements (see Parameter Measurement Information)
4.4.1
Master Mode Timing Requirements
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(1)
Delay time, SCLK
↑ to FS↓
5
ns
td(2)
Delay time, SCLK
↑ to DOUT
15
ns
tsu
Setup time, DIN, before SCLK low
5
ns
th
Hold time, DIN, after SCLK high
1/2T+5
ns
ten
Enable time, FS
↓ to DOUT
1/2T+5
ns
tdis
Disable time, FS
↑ to DOUT Hi-Z
CL = 20 pF
5
ns
td(3)
Delay time, MCLK
↓ to SCLK↑
L
10
ns
td(CH-FL)
Delay time, SCLK high to FS/FSD high (see Figure 5-1)
5
ns
td(CH-FH)
Delay time, SCLK high to FS/FSD high
5
ns
tw(H)
Pulse duration, MCLK high
12.5
ns
tw(L)
Pulse duration, MCLK low
12.5
ns
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