參數(shù)資料
型號： TLV320AIC10PFB
廠商： Texas Instruments, Inc.
英文描述： ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles
中文描述： 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁數(shù)： 8/46頁
文件大小： 452K
代理商： TLV320AIC10PFB
SLAS428 AUGUST 2004
www.ti.com
8
AUDIO INTERFACE TIMING DIAGRAMS
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
Figure 1. I
2
S/LJF/RJF Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 1)
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MIN
UNITS
MAX
25
MAX
15
td(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
LRCK delay time
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
10
6
ns
Fall time
10
6
ns
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
td(WS)
Figure 2. DSP Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 2)
All specifications at 25
°
C, DVDD = 1.8 V(1)
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MIN
UNITS
MAX
MAX
td(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
LRCK delay time
25
15
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
10
6
ns
Fall time
10
6
ns
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參數(shù)描述
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