參數(shù)資料
型號(hào)： TLV320AIC20KIPFBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁數(shù)： 31/52頁
文件大小： 981K
代理商： TLV320AIC20KIPFBRG4
www.ti.com
S/Sr
I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 0
Mode (5 Bit) + Index
Register Address
(3 Bit)
Ack
Control Register
Data (Write)
Ack
Control Register
Data (Write)
7 Bit
1 Bit
8 Bit
Increment Index Register Address
Default/Broadcast
(00000/11111)
Write Mode
To the Address Given
by Index Register
Address
To the Address Given
by Index Register
Address
S/Sr I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 1
Control Register Data
(Read)
Ack
Control Register
Data (Read)
Ack
7 Bit
1 Bit
8 Bit
Read Mode
From the Address Given
by Index Register Address
From the Address Given
by Index Register Address
Increment Index
Register Address
Increment Index
Register Address
S/Sr I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 0
Mode (5 Bit) + Index
Register Address
(3 Bit)
Ack
7 Bit
1 Bit
8 Bit
For Initializing Index Register Address
Stop
Register Map
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
S/Sr -> Start/Repeated Start.
Figure 33. Index Register Addresses
Each AIC2x codec consists of 2 channels. Each channel has 6 registers to enable the user to control various
components. Registers that control resources that are common across the two channels are shadowed. This
means that writing to the appropriate register in one channel automatically updates the contents of the same
register in the other channel to reflect the change. For example, writing to register 4 in channel 1 automatically
updates the contents of register 4 for channel 2 and vice versa. Refer to the individual register description for a
more detailed description of the exact register bits that are shadowed. Bits D15 through D13 represent the
control register address that is written with data carried in D7 through D0. Bit D12 determines a read or a write
cycle to the addressed register. When D12 = 0, a write cycle is selected. When D12 = 1, a read cycle is selected.
Bit D11 controls the broadcast mode as described above, in which the broadcast mode is enabled if D11 is set to
1. Always write 1s to the bits D10 through D8.
Table 3 shows the register map.
Table 3. Register Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Address
RW
BC
1
Control Register Content
Table 4. Register Addressing
REGISTER NO.
D15
D14
D13
REGISTER NAME
0
No operation
1
0
1
Control 1
2
0
1
0
Control 2
3
0
1
Control 3
4
1
0
Control 4
5
1
0
1
Control 5
6
1
0
Control 6
37
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