參數(shù)資料
型號(hào)： TLV320AIC24C
廠商： Texas Instruments, Inc.
英文描述： Layout and Grounding Guidelines for TLV320AIC2x
中文描述： 為TLV320AIC2x布局和接地指南
文件頁(yè)數(shù)： 13/46頁(yè)
文件大?。?/td> 452K
代理商： TLV320AIC24C
SLAS428 AUGUST 2004
www.ti.com
13
OPERATIONAUDIO DAC
Audio Analog I/O
The ’DAC26 has one mono audio input (MICIN) typically used for microphone recording, and an auxiliary input (AUX) that
can be used as a second microphone or line input. The ’DAC26 has an analog pass through mode where by the input from
the Mic and AUX input can be routed to any one of the analog output drivers. The dual audio output drivers have
programmable power level and can be configured to drive up to 325 mW into an 8-
speaker, or to drive 16-
stereo
headphones at over 30-mW per channel, or to provide a stereo line-level output. The power level of the output drivers is
controlled using bit D12 in control register REG05H/Page2. The ’DAC26 also has a virtual ground (VGND) output driver,
which can optionally be used to connect the return terminal of headphones, to eliminate the ac-coupling capacitors needed
at the headphone output. The VGND amplifier is controlled by bit D8 of REG05H/Page2. A special circuit has also been
included in the ’DAC26 to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered
down. The keyclick sound is used to provide feedback to the user when a particular button is pressed or item is selected.
The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and
amplitude.
Audio Digital Interface
Digital audio data samples are transmitted between the ’DAC26 and the audio processor via the serial bus (BCLK, LRCK,
DIN) that can be configured to transfer digital data in four different formats: right justified, left justified, I
2
S, and DSP. The
four modes are MSB-first and operate with variable word length of 16, 20, 24, or 32 bits. The digital audio serial bus of the
’DAC26 can operate in master or slave mode, depending on its register settings. The word-select signal (LRCK) and bit
clock signal (BCLK) are configured as outputs when the bus is in master mode. They are configured as inputs when the
bus is in slave mode. The LRCK is representative of the audio DAC sampling rate and is synchronized with DIN.
DAC SAMPLING RATE
The Audio Control 1 register (Register 00H, Page2) determines the sampling rates of the audio DAC, which is scaled
down from a reference rate (Fsref). When the audio DAC is powered up, it is configured by default as an I
2
S slave with
the DAC operating at Fsref.
WORD SELECT SIGNALS
The word select signal (LRCK) indicates the channel being transmitted:
LRCK = 0: left channel for I
2
S mode
LRCK = 1: right channel for I
2
S mode
For other modes see the timing diagrams below.
Bitclock (BCLK) Signal
In addition to flexibility as master or slave mode, the BCLK can also be configured in two transfer modes—256S and
Continuous Transfer Modes. These modes are set using bit D12/REG06h/Page2.
256S TRANSFER MODE
In the 256S mode, the BCLK rate always equals 256 times the maximum of the LRCK frequencies. In
the 256S mode, the DAC sampling rate equal to Fsref (as selected by bit D5D0/REG00h/Page2) and leftjustified
mode is not supported.
CONTINUOUS TRANSFER MODE
In the continuous transfer mode, the BCLK rate always equals two times the word length of the maximum of the LRCK
frequencies.
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