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參數資料
| 型號： | TLV320AIC25I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Layout and Grounding Guidelines for TLV320AIC2x |
| 中文描述： | 為TLV320AIC2x布局和接地指南 |
| 文件頁數： | 17/46頁 |
| 文件大?。?/td> | 452K |
| 代理商： | TLV320AIC25I |
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SLAS428 AUGUST 2004
www.ti.com
17
When PLL is enabled and D = 0, the following condition must be satisfied
80 MHz
MCLK
K
P
110 MHz
2 MHz
MCLK
P
20 MHz
4
J
55
When PLL is enabled and D
≠
0, the following condition must be satisfied
80 MHz
MCLK
K
P
110 MHz
10 MHz
MCLK
P
20 MHz
4
J
11
Example 1:
For MCLK = 12 MHz and Fsref = 44.1 kHz
P = 1, K = 7.5264
J = 7, D = 5264
Example 2:
For MCLK = 12 MHz and Fsref = 48.0 kHz
P = 1, K = 8.192
J = 8, D = 1920
STEREO AUDIO DAC
Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, digital
delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low
sample rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the
delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized
by keeping the upsampled rate constant at 128 x Fsref and changing the oversampling ratio as the input sample rate is
changed. For Fsref of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that
quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all
sample rates. Similarly, for Fsref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448
MHz.
Digital Audio Processing
The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, or speaker
equalization. The de-emphasis function is only available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The transfer
function consists of a pole with time constant of 50
μ
s and a zero with time constant of 15
μ
s. Frequency response plots
are given in the
Audio DAC Filter Frequency Responses
section of this data sheet. The de-emphasis filter can be enabled
or bypassed depending on bit D0 of register 05H/Page2.
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable coefficients (one
set per channel). The filter is implemented as cascade of two biquad sections with frequency response given by:
N0
2
N1
z
1
N2
z
2
32768
2
D1
z
1
D2
z
2
N3
2
N4
z
1
N5
z
2
32768
2
D4
z
1
D5
z
2
The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed depending on bit D1 of
register 05H/Page2. The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being
the most commonly used in portable audio applications. The default N and D coefficients in the part are given by:
N0 = N3 = 27619
N1 = N4 = 27034
N2 = N5 = 26461
D1 = D4 = 32131
D2 = D5 = 31506
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| TLV320AIC25IPFBR | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC25IPFBRG4 | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC26 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW POWER STEREP AUDIO CODEC WITH HEADPHONE / SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC |
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