TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
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SPI DIGITAL INTERFACE
All ’AIC26 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the
synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize
transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SPIDIN
(MOSI) pin under the control of the master serial clock. As the byte shifts in on the SPIDIN pin, a byte shifts out on the
SPIDOUT (MISO) pin to the master shift register.
The idle state of the serial clock for the ’AIC26 is low, which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The ’AIC26 interface is designed so that with a clock phase bit setting of 1 (typical
microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its SPIDOUT
pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the ’AIC26 only interprets
command words which are transmitted after the falling edge of SS.
OPERATIONAUXILIARY MEASUREMENT
Data Format
The ’AIC26 auxiliary output data is in unsigned binary format and can be read from the registers over the SPI interface.
Reference
The ’AIC26 has an internal voltage reference that can be set to 1.25 V or 2.5 V, through the reference control register.
The internal reference voltage should only be used in the single-ended mode for battery monitoring, temperature
measurement, and for measuring the auxiliary inputs.
An external reference can also be applied to the VREF pin, and the internal reference can be turned off.
Variable Resolution
The ’AIC26 provides three different resolutions for the A/D converter: 8-, 10- or 12-bits. Performing the conversions at lower
resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which lowers power
consumption.
Conversion Clock and Conversion Time
The ’AIC26 contains an internal 8-MHz clock, which is used to drive the state machines inside the device that perform the
many functions of the part. This clock is divided down to provide a clock to run the A/D converter. The division ratio for this
clock is set in the A/D converter control register. The ability to change the conversion clock rate allows the user to choose
the optimal value for resolution, speed, and power. If the 8-MHz clock is used directly, the A/D converter is limited to 8-bit
resolution; using higher resolutions at this speed may not result in accurate conversions. Using a 4-MHz conversion clock
is suitable for 10-bit resolution; 12-bit resolution requires that the conversion clock run at 1 or 2 MHz.
Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion clock speed,
however, plays an important role in the time it takes for a conversion to complete, as a certain number of internal clock cycles
is needed for proper sampling of the signal. Throughout this data sheet, internal and conversion clock cycles are used to
describe the times that many functions take to execute. Considering the total system design, these times must be taken
into account by the user.
When both the audio ADC and DAC are powered down, the auxiliary A/D uses an internal oscillator for conversions.
However, to save power whenever audio ADC or DAC are powered up, the internal oscillator is powered down and MCLK
and BCLK are used to clock the auxiliary A/D.
The ’AIC26 uses the programmed value of Page2, Reg 06H D13 and the PLL programmability to derive a clock from MCLK.
The various combinations are listed in Table 4.
Table 4. Conversion Clock Frequency
Page2, Reg 06H, D13 = 0
Page2, Reg 06H, D13 = 1
PLL enabled
MCLK
K
13
P
160
MCLK
K
17
P
192
PLL disabled
MCLK
13
Q
10
MCLK
17
Q
12