參數(shù)資料
型號(hào)： TLV320AIC28IRGZR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁數(shù)： 39/85頁
文件大?。?/td> 1053K
代理商： TLV320AIC28IRGZR
TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
44
REGISTER 01H: Status Register
BIT
NAME
RESET
VALUE
READ/
WRITE
FUNCTION
D15D14
DAV
10
R/W
Data Available. These two bits program the function of the DAV pin.
00 => Reserved
01 => Acts as data available (active low) only. The DAV goes low as soon as one set of ADC
conversion(s) is completed. For scan mode, DAV remains low as long as all the
appropriate registers have not been read out.
10 => Reserved
11 => Reserved
Note: D15D14 should be rpogrammed to 01 for the AIC28 to operate properly.
D13
PWRDN
0
R
ADC Power down status
0 => ADC is active
1 => ADC stops conversion and powers down
D12
0
R
Reserved
D11
DAVAIL
0
R
Data Available Status
0 => No data available.
1 => Data is available(i.e one set of conversion is done)
Note: This bit gets cleared only after all the converted data have been completely read out. This bit
is not valid in case of buffer mode.
D10D7
0
R
Reserved
D6
BSTAT
0
R
BAT Data Register Status
0 => No new data is available in BAT data register
1 => New data is available in BAT data register
Note: This bit gets cleared only after the converted data of BAT has been completely read out of the
register. This bit is not valid in case of buffer mode.
D5
0
R
Reserved
D4
AX1STAT
0
R
AUX1 Data Register Status
0 => No new data is available in AUX1data register
1 => New data is available in AUX1data register
Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D3
AX2STAT
0
R
AUX2 Data Register Status
0 => No new data is available in AUX2data register
1 => New data is available in AUX2data register
Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D2
T1STAT
0
R
TEMP1 Data Register Status
0 => No new data is available in TEMP1data register
1 => New data is available in TEMP1data register
Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D1
T2STAT
0
R
TEMP2 Data Register Status
0 => No new data is available in TEMP2data register
1 => New data is available in TEMP2data register
Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D0
0
R
Reserved
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