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SLOS631 – MARCH 2010
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3253) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the Application Reference Guide,
SLAU303Power Supply
The TLV320AIC3253 has four power-supply connections which allow various optimizations for low system power.
The four supply pins are LDOin, DVdd, AVdd and IOVDD. To power up the device, a digital supply in the range
of 1.26V to 1.95V is applied to the DVDD pin. The IOVDD voltage can be in the range of 1.1V - 3.6V. The analog
core supply can either be derived from the internal LDO accepting an LDOin voltage in the range of 1.9V to 3.6V,
or the AVDD pin can directly be driven with a voltage in the range of 1.5V to 1.95V.
For more detailed information see the TLV320AIC3253Application Reference Guide,
SLAU303Device Special Functions
The following special functions are available to support advanced system requirements:
Headset detection
Interrupt generation
Flexible pin multiplexing
For more detailed information see the Application Reference Guide,
SLAU303The TLV320AIC3253 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the
second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1152 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. Typical algorithms for the TLV320AIC3253 miniDSPs are active noise
cancellation, acoustic echo cancellation or advanced DSP sound enhancement algorithms.
Software
Software development for the TLV320AIC3253 is supported through TI's comprehensive PurePath Studio
Development Environment. A powerful, easy-to-use tool designed specifically to simplify software development
on the TLV320AIC3xxx miniDSP audio platform. The Graphical Development Environment consists of a library of
common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected
together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.
Please visit the TLV320AIC3253 product folder on www.ti.com to learn more about PurePath Studio and the
latest status on available, ready-to-use DSP algorithms.
Register Map Summary
Table 10. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2
0x00
0x02
Reserved Register
0
3
0x00
0x03
Reserved Register
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P&R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
Copyright 2010, Texas Instruments Incorporated
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