參數(shù)資料
型號: TLV320AIC32IRHBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 26/72頁
文件大?。?/td> 4594K
代理商: TLV320AIC32IRHBG4
www.ti.com
ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
INPUT IMPEDANCE AND VCM CONTROL
MICBIAS GENERATION
ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
TLV320AIC32
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
capability is useful in a cellphone, for example, when a separate FM radio device provides a stereo analog output
signal that needs to be routed to headphones. The TLV320AIC32 supports this in a low power mode by providing
a direct analog path through the device to the output drivers, while all ADCs and DACs can be completely
powered down to save power. When programmed correctly, the device can pass the signal LINE2L and LINE2R
to the output stage directly.
In addition to the input bypass path described above, the TLV320AIC32 also includes the ability to route the ADC
PGA output signals past the ADC, for mixing with other analog signals and then direction connection to the
output drivers. These bypass functions are described in more detail in the sections on output mixing and output
driver configurations.
The TLV320AIC32 includes several programmable settings to control analog input pins, particularly when they
are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
tri-state condition, such that the input impedance seen looking into the device is extremely high. Note, however,
that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any
voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS,
these protection diodes will begin conducting current, resulting in an effective impedance that no longer appears
as a tri-state condition.
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in Page-0/Reg-20 and 23. The user should ensure this option is disabled
when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, since it
can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC32 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for DC voltage measurement. The ac-coupling
capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 k
with an input level control setting of
0-dB, and increasing to approximately 80-k
when the input level control is set at –12 dB. For example, using a
0.1
F ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 Hz when the 0 dB input
level control setting is selected.
The TLV320AIC32 includes a programmable microphone bias output voltage (MICBIAS), capable of providing
output voltages of 2.0 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output current drive.
In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it
can be powered down completely when not needed, for power savings. This function is controlled by register
programming in Page-0/Reg-25.
The TLV320AIC32 has two fully differential line output drivers, each capable of driving a 10-k
differential load.
The output stage design leading to the fully differential line output drivers is shown in Figure 29 and Figure 30.
This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond
that already provided by the PGA gain and the DAC digital volume control.
The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage.
The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to
the output stage. Note that since both left and right channel signals are routed to all output drivers, a mono mix
of any of the stereo signals can easily be obtained by setting the volume controls of both left and right channel
signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through
register control.
32
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