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參數資料
| 型號： | TLV320DAC23IGQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 32-BIT DAC, PBGA80 |
| 封裝： | PLASTIC, MICRO, BGA-80 |
| 文件頁數： | 39/39頁 |
| 文件大?。?/td> | 664K |
| 代理商： | TLV320DAC23IGQER |
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16
1.5
Terminal Functions
TERMINAL
NAME
NUMBER
I/O
DESCRIPTION
NAME
GQE
PW
RHD
I/O
DESCRIPTION
AGND
5
15
12
Analog supply return
AVDD
4
14
11
Analog supply input. Voltage level is 3.3 V nominal.
BCLK
23
3
28
I/O
I2S serial-bit clock. In audio master mode, the DAC23 generates this signal and sends it to the
DSP. In audio slave mode, the signal is generated by the DSP.
BVDD
21
1
26
Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
CLKOUT
22
2
27
O
Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X
frequencies of XTI. Frequency selection is controlled by bit X in control register XX.
CS
12
21
18
I
Control port input latch/address select. For SPI control mode this input acts as the data latch
control. For 2-wire control mode this input defines the seventh bit in the device address field.
See Section 3.1 for details.
DIN
24
4
1
I
I2S format serial data input to the sigma-delta stereo DAC
DGND
20
28
25
Digital supply return
DVDD
19
27
24
Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND
32
11
8
Analog headphone amplifier supply return
HPVDD
29
8
5
Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
LHPOUT
30
9
6
O
Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1.0 VRMS.
Gain of –73 dB to 6 dB is provided in 1-dB steps.
LLINEIN
11
20
17
I
Left stereo-line input channel
LOUT
2
12
9
O
Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
LRCIN
26
5
2
I/O
I2S DAC-word clock signal. In audio master mode, the DAC23 generates this framing signal
and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.
MODE
13
22
19
I
Serial interface mode input. See Section 3.1 for details.
NC
1, 7, 8,
9, 17,
25, 27,
28
6, 7,
17,18
3, 4,
14, 15
Not Used—No internal connection
RHPOUT
31
10
7
O
Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is
1.0 VRMS. Gain of 73 dB to 6 dB is provided in 1-dB steps.
RLINEIN
10
19
16
I
Right stereo-line input channel
ROUT
3
13
10
O
Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
SCLK
15
24
21
I
Control port serial data clock. For both SPI and 2-wire control modes this is the serial clock
input. See Section 3.1 for details.
SDIN
14
23
20
I
Control port serial data input. For both SPI and 2-wire control modes this is the serial data input
and also is used to select the control protocol after reset. See Section 3.1 for details.
VMID
6
16
13
I
Midrail voltage decoupling input. 10-
F and 0.1-F capacitors should be connected in parallel
to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK
16
25
22
I
Crystal or external clock input. Used for derivation of all internal clocks on the DAC23.
XTO
18
26
23
O
Crystal output. Connect to external crystal for applications where the DAC23 is the audio timing
master. Not used in applications where external clock source is used.
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| TLV320DAC23IPW | 功能描述:音頻數/模轉換器 IC Low-Power Portable Aud Converter RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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| TLV320DAC23IPWRG4 | 功能描述:音頻數/模轉換器 IC Octal Bus Trnscvr With 3-State Outputs RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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