參數(shù)資料
型號(hào)： TLV320DAC23RHDR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 32-BIT DAC, PQCC28
封裝： GREEN, PLASTIC, QFN-28
文件頁(yè)數(shù)： 14/39頁(yè)
文件大小： 664K
代理商： TLV320DAC23RHDR
36
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and and the synchronization signal LRCIN.
BCLK is an output in master mode and an input in slave mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN (see
Figure 3-4).
LRCIN
BCLK
DIN
n
n1
0
1
n1
n
1/fs
Left Channel
Right Channel
1
0
MSB
LSB
Figure 34. Right Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN (see
Figure 3-5)
LRCIN
BCLK
DIN
n
n1
0
1
n1
n
1/fs
Left Channel
Right Channel
1
0
n
MSB
LSB
Figure 35. Left Justified Mode Timing
3.3.1.3 I2S Mode
In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN (see Figure 3-6).
LRCIN
BCLK
DIN
n
n1
0
1
n1
n
1/fs
Left Channel
Right Channel
1
0
MSB
LSB
1BCLK
Figure 36. I2S Mode Timing
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