參數(shù)資料
型號： TLV320DAC26IRHBR
英文描述： LOW POWER STEREO AUDIO DAC WITH HEADPHONE/SPEAKER AMPLIFIER
中文描述： 低功耗立體聲音頻DAC耳機(jī)/揚(yáng)聲器放大器
文件頁數(shù)： 43/46頁
文件大?。?/td> 452K
代理商： TLV320DAC26IRHBR
SLAS428 AUGUST 2004
www.ti.com
43
De-Emphasis Error at 48 ksps
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
0.1
0
0.5
1
Frequency Hz
1.5
2
2.5
G
De-Emphasis Error With Respect to Ideal Frequency Response For Fs = 48 kHz
x 104
PLL PROGRAMMING
The on-chip PLL in the ’DAC26 can be used to generate sampling clocks from a wide range of MCLK’s available in a system.
The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz). Frequency division generates
all other internal clocks. The table below gives a sample programming for PLL registers for some standard MCLK’s when
PLL is required. Whenever the MCLK is of the form of N x 128 x Fsref (N=2,3
…
,17), PLL is not required.
Fsref = 44.1 kHz
MCLK (MHz)
2.8224
P
1
J
32
D
0
ACHIEVED FSREF
44100.00
% ERROR
0.0000
5.6448
1
16
0
44100.00
0.0000
12
1
7
5264
44100.00
0.0000
13
1
6
9474
44099.71
0.0007
16
1
5
6448
44100.00
0.0000
19.2
1
4
7040
44100.00
0.0000
19.68
1
4
5893
44100.30
0.0007
48
4
7
5264
44100.00
0.0000
Fsref = 48 kHz
MCLK (MHz)
2.048
P
1
J
48
D
0
ACHIEVED FSREF
48000.00
% ERROR
0.0000
3.072
1
32
0
48000.00
0.0000
4.096
1
24
0
48000.00
0.0000
6.144
1
16
0
48000.00
0.0000
8.192
1
12
0
48000.00
0.0000
12
1
8
1920
48000.00
0.0000
13
1
7
5618
47999.71
0.0006
16
1
6
1440
48000.00
0.0000
19.2
1
5
1200
48000.00
0.0000
19.68
1
4
9951
47999.79
0.0004
48
4
8
1920
48000.00
0.0000
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