參數(shù)資料
型號: TLV5606CDGKG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 9 us SETTLING TIME, 10-BIT DAC, PDSO8
封裝: GREEN, PLASTIC, MSOP-8
文件頁數(shù): 5/27頁
文件大?。?/td> 636K
代理商: TLV5606CDGKG4
TLV5606
2.7V TO 5.5V LOW POWER 10BIT DIGITALTOANALOG
CONVERTERS WITH POWER DOWN
SLAS259B DECEMBER 1999 REVISED APRIL 2004
13
WWW.TI.COM
APPLICATION INFORMATION
TLV5606 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example how to connect the TLV5606 to a TMS320C203 DSP. The serial interface of the
TLV5606 is ideally suited to this configuration, using a maximum of four wires to make the necessary
connections. In applications where only one synchronous serial peripheral is used, the interface can be
simplified even further by pulling CS low all the time as shown in the figure.
FS
DIN
SCLK
OUT
REFIN
CS AGND
VDD
REF
FS
DX
CLKX
TMS320C203
TLV5606
RLOAD
Figure 17. TLV5606 to DSP Interface
software
No setup procedure is needed to access the TLV5606. The output voltage can be set using just a single
command.
out
data_addr, SDTR
where data_addr points to an address location holding the control bits and the 12 data bits providing the output
voltage data. SDTR is the address of the transmit FIFO of the synchronous serial port.
The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp
with the TLV5606.
A timer interrupt is generated every 205
s. The corresponding interrupt service routine increments the output
code (stored at 0x0064) for the DAC, adds the DAC control bits to the four most significant bits, and writes the
new code to the TLV5606. The resulting period of the saw waveform is:
π = 4096 × 205 E-6 s = 0.84 s
;***************************************************************************************
;* Title
: Ramp generation with TLV5606
*
;* Version : 1.0
*
;* DSP
: TI TMS320C203
*
;*
(1998) Texas Instruments Incorporated
*
;***************************************************************************************
; I/O and memory mapped regs
.include ”regs.asm”
; vectors
.ps
0h
b
start
b
INT1
b
INT23
b
TIM_ISR
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