參數(shù)資料
型號(hào)： TLV5608IYER
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PBGA20
封裝： WAFER CHIP SCALE, 20 PIN
文件頁(yè)數(shù)： 12/17頁(yè)
文件大?。?/td> 345K
代理商： TLV5608IYER
TLV5610IYE
TLV5608IYE
SLAS393 OCTOBER 2003
www.ti.com
4
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range unless otherwise noted(1)
OUTPUT SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 k
0
AVDD0.4
V
Output load regulation accuracy
RL = 2 k vs 10 k
±0.3
%Full
Scale V
REFERENCE INPUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
0
AVDD
V
RI
Input resistance
100
k
Ci
Input capacitance
5
pF
Reference input bandwidth
Vref = 0.4 Vpp + 2.048 Vdc, Input code = 0x800
Fast
2.2
MHz
Reference input bandwidth
Vref = 0.4 Vpp + 2.048 Vdc, Input code = 0x800
Slow
1.9
MHz
Reference feedthrough
Vref = 2 Vpp at 1 kHz + 2.048 Vdc (see Note 1)
84
dB
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = DVDD
1
A
IIL
Low-level digital input current
VI = 0 V
1
A
Ci
Input capacitance
8
pF
DIGITAL OUTPUTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level digital output voltage
RL = 10 k
2.6
V
VOL
Low-level digital output voltage
RL = 10 k
0.4
V
Output voltage rise time
RL = 10 k, CL = 20 pF, Includes propogation delay
7
20
ns
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ts(FS)
Output settling time, full scale
RL = 10 k,
CL = 100 pF, See Note 1
Fast
1
3
s
ts(FS)
Output settling time, full scale
RL = 10 k,
CL = 100 pF, See Note 1
Slow
3
7
s
ts(CC)
Output settling time, code to code
RL = 10 k,
CL = 100 pF, See Note 2
Fast
0.5
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,
CL = 100 pF, See Note 2
Slow
1
2
s
SR
Slew rate
RL = 10 k,
CL = 100 pF, See Note 3
Fast
4
10
V/ s
SR
Slew rate
RL = 10 k,
CL = 100 pF, See Note 3
Slow
1
3
V/
s
Glitch energy
See Note 4
4
nVs
Channel crosstalk
10 kHz sine, 4 VPP
90
dB
(1)Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x80 to 0xFFF
and 0xFFF to 0x080 respectively. Assured by design; not tested.
(2)Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. The
max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(3)Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage.
(4)Code transition: TLV5610IYE 0x7FF to 0x800, TLV5608IYE 0x7FC to 0x800.
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