參數(shù)資料
型號: TLV5613IPWR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 20/23頁
文件大?。?/td> 447K
代理商: TLV5613IPWR
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
digital inputs
MIN
NOM
MAX
UNIT
tsu(D)
Setup time, data ready before positive WE edge
9
ns
tsu(CS-WE)
Setup time, CS low before positive WE edge
13
ns
tsu(A)
Setup time, address bits A0, A1
17
ns
th(D)
Hold time, data held after positive WE edge
0
ns
tsu(WE-LD)
Setup time, positive WE edge before LDAC low
0
ns
tw(WE)
Pulse duration, WE high
25
ns
tw(LD)
Pulse duration, LDAC low
25
s
PARAMETER MEASUREMENT INFORMATION
X
Data
X
Address
X
tsu(D)
tsu(A)
th(D)
tw(WE)
tsu(WE-LD)
tw(LD)
tsu(CS-WE)
D(0–7)
A(0–1)
CS
WE
LDAC
Figure 1. Timing Diagram
相關(guān)PDF資料
PDF描述
TLV5613IDWRG4 PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5613IPWG4 PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5613CPWG4 PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5613CDWG4 PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5613IPWRG4 PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20
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