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參數資料
| 型號： | TLV5614IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數： | 31/34頁 |
| 文件大小： | 737K |
| 代理商： | TLV5614IDRG4 |
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TLV5614
2.7-V TO 5.5-V 12-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Output slew rate
CL = 100 pF, RL = 10 k,
VO 10% to 90%
Fast
5
V/
s
SR
Output slew rate
VO = 10% to 90%,
Vref = 2.048 V, 1024 V
Slow
1
V/
s
t
Output settling time
To
± 0.5 LSB, CL = 100 pF,
Fast
3
5.5
s
ts
Output settling time
To
± 0.5 LSB, CL = 100 F,
RL = 10 k, See Notes 12 and 14
Slow
9
20
s
t
Output settling time code to code
To
± 0.5 LSB, CL = 100 pF,
Fast
1
s
ts(c)
Output settling time, code to code
To
± 0.5 LSB, CL = 100 F,
RL = 10 k, See Note 13
Slow
2
s
Glitch energy
Code transition from 7FF to 800
10
nV-sec
SNR
Signal-to-noise ratio
Sinewave generated by DAC,
R f
lt
1 024 t 3 V
d 2 048 t 5 V
74
S/(N+D)
Signal to noise + distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS,
66
dB
THD
Total harmonic distortion
fs = 400 KSPS,
fOUT = 1.1 kHz sinewave,
CL = 100 pFRL =10k
–68
dB
SFDR
Spurious free dynamic range
CL = 100 pF,
RL = 10 k,
BW = 20 kHz
70
NOTES: 12. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
ofFFF hex to 080 hex for 080 hex to FFF hex.
13. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
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