- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98260 > TLV5625IDRG4 (TEXAS INSTRUMENTS INC) SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 PDF資料下載
參數(shù)資料
| 型號： | TLV5625IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 212K |
| 代理商： | TLV5625IDRG4 |
TLV5625
2.7V TO 5.5V LOW POWER DUAL 8BIT DIGITALTOANALOG
CONVERTER WITH POWER DOWN
SLAS233D JULY 1999 REVISED JULY 2002
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by the reference) is given by:
2REF
CODE
2n
[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n1, where
n=8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format
section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI
, and Microwire.
TMS320
DSP FSX
CLKX
DX
TLV5625
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5625
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5625
SCLK
DIN
CS
Figure 12. Three-Wire Interface
Notes on SPI
and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI
and Microwire) two write operations
must be performed to program the TLV5625. After the write operation(s), the holding registers or the control
register are updated automatically on the 16th positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax +
1
t
whmin ) twlmin
+ 20 MHz
The maximum update rate is:
f
updatemax +
1
16 t
whmin ) twlmin
+ 1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5625 should also be considered.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV5625IDG4 | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| TLV5625IDR | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| TLV5625CD | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| TLV5625CDR | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| TLV5626CD | SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 8-BIT DAC, PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV5626 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN |
| TLV5626CD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 8bit DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5626CD | 制造商:Texas Instruments 功能描述:D/A Converter (D-A) IC |
| TLV5626CDG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 1 us Dual DAC Serial Input RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5626CDR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 1 us Dual DAC Serial Input RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。