參數(shù)資料
型號(hào): TLV5633C
廠商: Texas Instruments, Inc.
英文描述: 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
中文描述: 2.7 V至5.5 V低功耗12位數(shù)字到模擬,具有內(nèi)部參考和斷電變換器
文件頁(yè)數(shù): 12/22頁(yè)
文件大?。?/td> 301K
代理商: TLV5633C
TLV5633C, TLV5633I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS190 – MARCH 1999
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5633 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by:
2 REF
CODE
0 1000
[V]
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written
to one of the DAC holding latches (MSW, LSW) or the control register depends on the address bits A1 and A0.
LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held
low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be
approximately a 5 ns delay after the positive WE edge before driving LDAC low. Two more asynchronous inputs,
SPD and PWR control the settling times and the power-down mode:
SPD:
PWR:
Speed control
Power control
1
fast mode
1
normal operation
0
slow mode
0
power down
It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the
control register. The following tables list the possible combinations of control signals and control bits.
PIN
SPD
0
BIT
SPD
0
MODE
Slow
0
1
Fast
1
0
Fast
1
1
Fast
PIN
PWR
0
BIT
PWD
0
POWER
Down
0
1
Down
1
0
Normal
1
1
Down
PIN
LDAC
0
BIT
LATCH
RLDAC
0
Transparent
0
1
Transparent
1
0
Hold
1
1
Transparent
相關(guān)PDF資料
PDF描述
TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
TLV5636D 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
TLV5636DGK 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
TLV5637D 2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
tlv5639(中文) 2.7V to 5.5V Low Power 12-Bit Digital-to-Analog Converters with Internal Reference and Power Down(2.7V-5.5V,12位低功耗,帶自動(dòng)掉電和內(nèi)部基準(zhǔn)的DAC)
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