參數(shù)資料
型號(hào): TLV5637CDR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 10-BIT DAC, PDSO8
封裝: GREEN, PLASTIC, MS-012AA, SOIC-8
文件頁數(shù): 3/21頁
文件大?。?/td> 422K
代理商: TLV5637CDR
www.ti.com
DATA FORMAT
Register Select Bits
Data Bits: DAC A, DAC B and BUFFER
Data Bits: CONTROL
SLAS224C – JUNE 1999 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
The 16-bit data word for the TLV5637 consists of two parts:
Program bits (D15..D12)
New data (D11..D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R1
SPD
PWR
R0
12 Data bits
SPD: Speed control bit
1
→ fast mode
0
→ slow mode
PWR: Power control bit
1
→ power down
0
→ normal operation
The following table lists the possible combination of the register select bits:
R1
R0
REGISTER
0
Write data to DAC B and BUFFER
0
1
Write data to BUFFER
1
0
Write data to DAC A and update DAC B with BUFFER content
1
Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
New DAC Value
0
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
REF1
REF0
X: don't care
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
11
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TLV5637IDRG4 SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 10-BIT DAC, PDSO8
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