參數(shù)資料
型號(hào): TLV5638MFK
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CQCC20
封裝: HERMETIC SEALED, CERAMIC, LCC-20
文件頁(yè)數(shù): 18/23頁(yè)
文件大?。?/td> 531K
代理商: TLV5638MFK
www.ti.com
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
MIN
NOM
MAX
UNIT
VDD = 5 V
4.5
5
5.5
V
Supply voltage, VDD
VDD = 3 V
2.7
3
3.3
V
Power on reset, POR
0.55(1)
2(1)
V
VDD = 2.7 V
2
V
High-level digital input voltage, VIH
VDD = 5.5 V
2.4
VDD = 2.7 V
0.6
V
Low-level digital input voltage, VIL
TLV5638C and TLV5638I
1
VDD = 5.5 V
V
TLV5638Q and TLV5638M
0.8
Reference voltage, Vref to REF terminal
VDD = 5 V (2)
AGND
2.048
VDD-1.5
V
Reference voltage, Vref to REF terminal
VDD = 3 V (2)
AGND
1.024
VDD-1.5
V
Load resistance, RL
2
k
Load capacitance, CL
100
pF
Clock frequency, fCLK
20
MHz
TLV5638C
0
70
TLV5638I
40
85
Operating free-air temperature, TA
°C
TLV5638Q
40
125
TLV5638M
55
125
(1)
This parameter is not tested for Q and M suffix devices.
(2)
Due to the x2 output buffer, a reference input voltage
≥ (V
DD-0.4 V)/2 causes clipping of the transfer function. The output buffer of the
internal reference must be disabled, if an external reference is used.
over recommended operating conditions, V
ref = 2.048 V, Vref= 1.024 V (unless otherwise noted)
POWER SUPPLY
TLV5638C, I
TLV5638M
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Fast
4.3
7
VDD= 5 V,
mA
Int. ref.
Slow
2.2
3.6
Fast
3.8
6.3
VDD = 3 V,
mA
No load,
Int. ref.
Slow
1.8
3.0
IDD
Power supply current
All inputs = AGND or VDD,
Fast
3.9
6.3
VDD = 5 V,
DAC latch = 0x800
mA
Ext. ref.
Slow
1.8
3.0
Fast
3.5
5.7
VDD = 3 V,
mA
Ext. ref.
Slow
1.5
2.6
Power-down supply current
0.01
10
A
Zero scale, (1)
65
PSRR
Power supply rejection ratio
dB
Full scale, (2)
65
(1)
Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) -
EZS(VDDmin))/VDDmax]
(2)
Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) -
EG(VDDmin))/VDDmax]
4
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