參數(shù)資料
型號(hào)： TLV5638MJGB
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CDIP8
封裝： HERMETIC SEALED, CERAMIC, DIP-8
文件頁數(shù)： 3/23頁
文件大小： 531K
代理商： TLV5638MJGB
www.ti.com
DATA FORMAT
REGISTERED SELECT BITS
DATA BITS: DAC A, DAC B and BUFFER
DATA BITS: CONTROL
REFERENCE BITS
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
APPLICATION INFORMATION (continued)
The 16-bit data word for the TLV5638 consists of two parts:
Program bits (D15..D12)
New data (D11..D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R1
SPD
PWR
R0
12 Data bits
SPD: Speed control bit
1
→ fast mode
0
→ slow mode
PWR: Power control bit
1
→ power down
0
→ normal operation
The following table lists the possible combination of the register select bits:
R1
R0
REGISTER
0
Write data to DAC B and BUFFER
0
1
Write data to BUFFER
1
0
Write data to DAC A and update DAC B with BUFFER content
1
Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
New DAC Value
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
REF1
REF0
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
REF1
REF0
REFERENCE
0
External
0
1
1.024 V
1
0
2.048 V
1
External
CAUTION:
If external reference voltage is applied to the REF pin, external reference MUST
be selected.
11
相關(guān)PDF資料
PDF描述
TLV5638CDRG4 SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5638IDRG4 SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5638CDG4 SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5638IDG4 SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8
TLV5638MJG SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CDIP8
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