- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98262 > TLV571IDWG4 (TEXAS INSTRUMENTS INC) 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 PDF資料下載
參數(shù)資料
| 型號： | TLV571IDWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 479K |
| 代理商： | TLV571IDWG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Internal
Clock
CLK
CS
RD
INT/EOC
MUX
8-BIT
SAR ADC
Input Registers
and Control Logic
WR
CSTART
REFP
Three
State
Latch
AVDD
D0 – D5
D6/A0
D7/A1
REFM
DVDD
DGND
AGND
AIN
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
21
Analog ground
AIN
23
I
ADC analog input
AVDD
22
Analog supply voltage, 2.7 V to 5.5 V
A0/D6
16
I/O
Bidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 for
initialization.
A1/D7
17
I/O
Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 for
initialization.
CLK
4
I
External clock input
CS
1
I
Chip select. A logic low on CS enables the TLV571.
CSTART
18
I
Hardware sample and conversion start input. The falling edge of CSTART starts sampling and the rising edge
of CSTART starts conversion.
DGND
5, 8, 9
Digital ground
DVDD
6
Digital supply voltage, 2.7 V to 5.5 V
D0 – D5
10 –15
I/O
Bidirectional 3-state data bus
INT/EOC
7
O
End-of-conversion/interrupt
NC
24
Not connected
RD
3
I
Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM
20
I
Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.
REFP
19
I
Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by the difference
between the voltage applied to REFP and REFM.
WR
2
I
Write data. A rising edge on the WR latches in configuration data when CS is low. When using software
conversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,
the ADC in nonprogrammable (hardware configuration mode).
相關PDF資料 |
PDF描述 |
|---|---|
| TLV571IDW | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IPWG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IPW | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV5734PAG | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
| TLV5734PAGG4 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV571IDWR | 功能描述:模數(shù)轉換器 - ADC 8-Bit 1.25 MSPS Single Ch. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV571IDWRG4 | 功能描述:模數(shù)轉換器 - ADC 8-Bit 1.25 MSPS Single Ch. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV571IPW | 功能描述:模數(shù)轉換器 - ADC 8bit SAR A/D RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV571IPWG4 | 功能描述:模數(shù)轉換器 - ADC 8-Bit 1.25 MSPS Single Ch. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV571PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER |
發(fā)布緊急采購，3分鐘左右您將得到回復。