參數(shù)資料
型號: TLV571IDWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: GREEN, PLASTIC, SOIC-24
文件頁數(shù): 5/28頁
文件大?。?/td> 429K
代理商: TLV571IDWRG4
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
software START conversion (continued)
signal-to-noise ratio + distortion (SINAD)
Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.
DSP interface
The TLV571 is a 8-bit single input channel analog-to-digital converter with throughput up to 1.25 MSPS at 5 V
and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughput, the ADC must be clocked at 20 MHz. Likewise
to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The TLV571 can be easily interfaced
to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin connections to interface the TLV571 to the
TMS320C6x DSP.
Address
Decoder
EN
A0–A15
TMS320C6X
HW
HR
INTx
D0– D15
D0– D7
CS
WR
RD
EOC
TLV571
REF
AIN
REFP
REFM
Figure 8. TMS320C6x DSP Interface
相關(guān)PDF資料
PDF描述
TLV571IDWR 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV571IPWR 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV571IDWG4 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV571IDW 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
TLV571IPWG4 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
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