參數(shù)資料
型號(hào): TLV571IPW
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù): 3/28頁(yè)
文件大小: 479K
代理商: TLV571IPW
TL
V571
2.7
V
T
O
5.5
V
,1-CHANNEL,
8-BIT
P
ARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTER
SLAS239A
SEPTEMBER
1999
REVISED
FEBRUAR
Y
2000
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
11
software START conversion (continued)
internal clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.
OR
Auto Powerdown
ADC
CS
WR
RD
INTCLK
D[0:7]
INT
EOC
Config
Data
ADC
Data
tsu(CSL_WRL)
t
h(WRH_CSH)
t(sample)
tsu(DAV_WRH)
t
h(WRH_DAV)
tc
t su(CSL_RDL)
th(RDH_CSH)
ten(RDL_DAV)
t
dis(RDH_DAV)
tc
t
(STARTOSC)
t(STARTOSC)
t(sample)
45
6
0
4
5
015
15
Auto Powerdown
Figure 7. Input Conversion – Software Start, Internal Clock
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