參數(shù)資料
型號(hào): TLV987CPFB
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 285K
代理商: TLV987CPFB
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 3 V, ADCCLK = 27 MHz (unlessotherwise noted)
reference voltages
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal bandgap voltage reference
1.43
1.5
1.58
V
Temperature coefficient
100
ppm/
°C
Voltage reference noise
0.5
LSB
Positive reference voltage, ADC Ref+
Externally decoupled
1.8
2
2.2
V
Negative reference voltage, ADC Ref–
Externally decoupled
0.8
1
1.2
V
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS
IIH
High-level input current
DIVDD = 3 V
–10
10
A
IIL
Low-level input current
DIVDD = 3 V
–10
10
A
Ci
Input capacitance
5
pF
LOGIC OUTPUTS
VOH
High-level output voltage
IOH = 50 A, DIVDD = 3 V
DIVDD–0.4
V
VOL
Low-level output voltage
IOL = 50 A, DIVDD = 3 V
0.4
V
IOZ
High-impedance output current
–10
10
A
C
Output capacitance
5
pF
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(SR)
Pulse duration, SR
50% to 50%
10
ns
tw(SV)
Pulse duration, SV
50% to 50%
10
ns
tsu1
Setup time, OBCLP
↓ before ADCCLK ↑
Minimum 0.25
× ADCCLK clock cycle
th2
Hold time, ADCCLK
↓ after OBCLP ↑
td
Delay time, ADCCLK
↓ to ADCOUT valid
4
9
ns
tsu2
Setup time, CS
↓ before SCLK ↑
0
ns
th1
Hold time, SCLK
↓ after CS ↑
5
ns
0
5
10
15
20
25
30
35
40
0
28
56
84
112 140 168 196 224 252 280 308 336 364 392 420 448 476 504
Gain
dB
PGA – Gain Code
Figure 1. TLV987 PGA Gain Code vs Gain
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