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參數(shù)資料
| 型號(hào)： | TLV990-40PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大小： | 418K |
| 代理商： | TLV990-40PFBG4 |
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TLV99040
3V, 10BIT, 40MSPS AREA CCD ANALOG FRONT END
SLAS326A JANUARY 2001 REVISED MARCH 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
REGISTER DEFINITION
test register format
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TB9
TB8
TB7
TB6
X
TB3
TB2
X
Default register value =0110000000
These bits must be set to 1011 for 40 MSPS
test register description
BIT
NAME
DESCRIPTION
D9D6
TB9TB6
These four bits are used to program internal DC bias current. The bias current programming uses the following equation:
Ibias = 8 A + (code) × 2 A
Hence, Ibias varies from 8 A (code=0000) to 38 A (code=1111), with a linear step of 2 A.
Default code is 0110. These bits must be set to 1011 for 40 MSPS
D5, D4
Reserved
D3
TB3
1 – use external reference, power down internal reference
0 – use internal reference (default)
D2
TB2
This bit selects test input mode.
0 Single-ended input on CCDIN pin,
1 Differential input on both CCDIN and VIDEOIN pins
D1, D0
Reserved
PRINCIPLES OF OPERATION
CCD mode operation
The output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. The
CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting
two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor and
obtains the voltage difference between the CCD reference level and the video level of each pixel. Two
sample/hold control pulses (SR and SV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLV990-40. The ac-coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990-40 is
set to 1.2 V. Normally, CLCCD is applied at sensor’s line rate. A capacitor, with a value ten times larger than
that of the input ac-coupling capacitor, should be connected between the CLREF pin and the AGND.
When operating the TLV990-40 at its maximum speed, the CCD internal source resistance should be smaller
than 50
. Otherwise CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB
by programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit resolution
on a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation,
Gain = PGA code
× 0.045 dB
Where PGA code has a range of 0 to 767.
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